Commit 0a72e16c authored by Hellwig Geisse's avatar Hellwig Geisse
Browse files

update README

parent e095d21e
Welcome to Oberon-V2!
This is a re-implementation of "Project Oberon", Version 2 on N. Wirth's
Processor RISC5 (not to be confused with RISC-V).
This is a re-implementation of "Project Oberon", version 2, for
Niklaus Wirth's processor RISC5 (not to be confused with RISC-V).
The package also contains a RISC5 simulator and an implementation
of the processor and its peripherals in Verilog, ready to run on
an FPGA board (Terasic DE2-115).
Have fun!
Please consult the file STATUS in order to learn which parts of
the project have already been completed, and what remains to be
done.
If you have any questions, don't hesitate to contact me by email:
hellwig.geisse@mni.thm.de
Have fun!
Hellwig
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